1. Field of the Invention
This invention relates generally to a semiconductor device and, more particularly, to a semiconductor device having a buried wiring lead (wire lead) structure. This invention also relates to methodology of fabricating a semiconductor device of the type employing the buried wiring lead structure.
2. Description of Related Art
Metal wiring lines or leads are used to achieve electrical interconnection among elements of a semiconductor integrated circuit (IC) chip. Traditionally such on-chip metal wiring leads are typically manufacturable by patterning a metal film made of aluminum (Al) or else as formed on or above an electrically insulative dielectric film using lithography and anisotropic etching techniques in combination. As the circuit elements decrease in size due to the quest for higher integration in the chip, the wiring leads are becoming smaller in line width and in marginal spacing (pitch). This miniaturization makes it difficult to bury a dielectric film in space between patterned leads. An approach to avoiding this difficulty is to make use of a damascene method in place of prior known Al lead formation methods. The damascene method is the one that processes or micromachines a dielectric film to form therein a wiring lead groove and then buries conductive material, such as copper (Cu) or the like, in this groove by metal plating techniques.
In addition, in cases where capacitive elements of large capacitance are required within IC chips, metal-insulator-metal (MIM) capacitors are employed from time to time in lieu of conventional silicon-insulator-silicon (SIS) capacitors. MIM capacitors are typically designed to have a lamination or multilayer structure of upper and lower metallic layers with a dielectric film interposed between them. Preferably in this case, electrodes of such MIM capacitors are fabricated at the same time that on-chip leads are formed.
See FIGS. 13 to 16. These diagrams illustrate, in cross-section, some of major steps in the process for simultaneously forming a MIM capacitor and its associative Cu wiring lead by the damascene method. The simultaneous MIM-capacitor/Cu-lead fabrication process has been disclosed, for example, in Published Unexamined Japanese Patent Application No. 2001-36010 (“JP-A-2001-36010”). Firstly, as shown in FIG. 13, a silicon substrate 1 is prepared. After a dielectric film 2 is formed on the substrate 1, use anisotropic etch techniques to form grooves 3a, 3b simultaneously in the dielectric film 2. The groove 3a is for use with a buried on-chip lead wire. The other groove 3b is in a capacitor region of substrate 1 and is for formation of an embedded capacitor. After having formed a barrier metal (not shown), form by Cu plating methods a wiring lead 4a and a capacitor lower electrode 4b so that these are buried in the wire groove 3a and capacitor groove 3b respectively as shown in FIG. 14. Then, form a capacitor dielectric film 5 made of silicon nitride (SiN) or the like and a capacitor upper electrode film 6 made of TIN or the like, which is laminated on the film 5. Next, sequentially apply etching to the upper electrode film 6 and capacitor dielectric film 5 to thereby form a capacitor as shown in FIG. 15. Thereafter as shown in FIG. 16, deposit an inter-layer dielectric (ILD) film 7 on the entire surface of resultant device structure. Then, again use the damascene method to form contact portions 8a, 8b and an upper-level wiring lead 9 as buried in the ILO film 7.
Unfortunately the prior art Cu-damascene method stated above is encountered with several problems which follow.
First, as shown in FIG. 15, the capacitor is formed in the state that it is projected from the surface of the dielectric film 2 on Si substrate 1. Accordingly, a need is felt to apply additional or extra planarization processing to the ILD film 7 shown in FIG. 16 once after this film is formed. In view of the fact that the initial Cu damascene wiring lead burying process per se requires planarization, at least two planarization steps are required in the process. Practically, chemical mechanical polishing (CMP) techniques are used for such planarization.
Second, as shown in FIG. 16, the contact portions 8a-8b associated with the upper-level wiring lead 9 are different in depth from each other. This depth difference can cause unwanted over-etching at a shallower one, i.e. contact 8b, during formation of contact holes in ILD film 7. To suppress etching at its underlayer, a significant etching selection ratio is required between the dielectric film and its underlying layer.
Third, the Cu lead 4a can unintentionally be oxidized on its surface exposed to a corresponding contact hole during formation of the upper lead 9's contact holes by anisotropic etching, which would result in an increase in electrical resistivity.